It is software (packet) level splitting, aka when one device sends a packet it will send to vesc receive response and send it back to that device if at that moment another device sent a packet it will be delayed until previous device gets finished and etc Because of speeds there shouldn’t be much lags
This is kinda like your home network switch or router or etc works
This a game changer! So if I split the JST connected to the UART port in 2. I can connect both the devices. At the end a millsec delay in the telemetry won’t change the world.
Ya, thats what I am leaning towards as well. It’s not the most compact it could get in terms of device size, but the cables would sit nicely in a build which is probably the most important when trying to cram everything in.
I ordered the v2 PCBs for the 2 way splitter and the v1 PCBs for the 3 way splitter last night. I should be recieving them mid next week. It will likely take me a week or two to solder them up and test them. Once I am happy with the results, I will begin beta testing. I currently have 5 people waiting to become beta testers. I think I will do between 10 and 15 testers max.
@Wisp I clicked on the notification for this thread and read your name as part of the title and thought oh cool! He named the project something, thats a cool name! The Wisp UART splitter lolol
Unfortunately, due to a family emergency this last weekend, I was not able to complete the updates to the UART Splitter FW in the time frame I wanted. I was going to finished the updates and start shipping units before I leave for vacation tomorrow, but I will not be able to now. I will be back next Tuesday (7/9), will finish up the FW, and will begin shipping the beta kits shortly after.
I made some more progress today in implementing the changes needed before beta testing, but I also ran into a new issue.
When getting the Firefly remote to work, I realized that it communicates using 5v not 3.3v logic levels. The SAMD21 pins arent 5v tolerant (even though I’ve had no issue with 5v so far) but this can be solved by using series resistors on the RX pin of the external device ports.
The issue I’m having trouble figuring out is that the RX pin of the Firefly is getting pulled up to 5v internally, and when the splitter tries driving that pin low, it only pulls it down to ~2v. This isn’t always low enough for the Firefly receiver to recognize the 0 bits. Does anyone have ideas on how I can fix this in the receiver SW (possibly by removing the pull-up) or in HW?
I figured out the cause of the issue with sending data to the Firefly reciever. The reciever is based on an arduino clone which has a USB to Serial convert IC on board. That IC pulls the RX and TX pins up to 5v with a 1k resistor no matter what pin configuration the micro is programmed with. This combined with the fact that the SAMD21 drives it’s UART TX output has the configuration below means that the RX pin of the reciever is monitoring the middle of a voltage divider and cannot be pulled lower than ~2v.
I would like to make the splitter as plug n’ play as possible and requiring a logic level shifter for certain devices like this defintely wouldnt fit that, but it seems thats the only option atm.